A high-speed FPGA signal processing pipeline built in Xilinx Vivado, featuring a pipelined FFT core and real-time configurable filters, designed for hands-on ECE lab experimentation.
Software-based signal processing hits a wall when sample rates climb into the megahertz range — that's where dedicated hardware pipelines take over. This project implements a real-time FFT and filtering pipeline directly on FPGA fabric using VHDL, targeting a Xilinx Artix-7 development board.
The core is a pipelined radix-2 FFT engine, feeding into a configurable FIR filter bank. Everything is built to run at full sample-rate throughput with no software bottleneck — a design constraint that shapes every stage, from fixed-point arithmetic to butterfly-stage pipelining.
Beyond the pipeline itself, this project became a teaching tool: it's used in ECE lab sessions to let students visualize, in real hardware, what a textbook FFT and filter actually look like when clocked at real speed.
Fully pipelined FFT core sustains full sample-rate throughput with no software bottleneck.
Runtime-adjustable filter coefficients let users reshape the frequency response live.
Careful fixed-point scaling balances precision against FPGA resource usage.
Live frequency-domain output streamed to a host display for immediate visualization.
Packaged with a lab manual, used in coursework to teach DSP concepts on real hardware.
FFT and filter stages built as reusable VHDL modules for future project reuse.
A simulated time-domain waveform morphing into its frequency-domain spectrum — click to switch views, just like toggling the FPGA output mode.
I take on consultancy and freelance electronics projects — from prototype to production.
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